A low power sinusoidal clock
نویسندگان
چکیده
This paper describes a low power clock distribution that utilizes sinusoidal clock waveforms and proposes registers that are able to cope with the overlapping clock edges. We can report power savings of 30% to 70% compared with conventional clocking schemes while maintaining traditional static CMOS design styles and logic levels.
منابع مشابه
Design of an Ultra Low Power Clock Gating D Flip-Flop Using Quasi-Static Energy Recovery Logic
This paper presents low power clock gating adiabatic D flip-flop using single phase sinusoidal power clock scheme. We propose the clock gated single phase Quasi-Static Energy Recovery Logic (QSERL) D flip-flop at 90nm CMOS technology. In the previously proposed QSERL logic, two phase sinusoidal power clocks were used that increased the hardware complexity and clocking issues. In this paper, sin...
متن کاملHigh-performance and Low-power Clock Branch Sharing Pseudo-NMOS Level Converting Flip-flop
Multi-Supply voltage design using Cluster Voltage Scaling (CVS) is an effective way to reduce power consumption without performance degradation. One of the major issues in this method is performance and power overheads due to insertion of Level Converting Flip-Flops (LCFF) at the interface from low-supply to high-supply clusters to simultaneously perform latching and level conversion. In this p...
متن کاملA Noble Design of Energy Recovery Flip-Flops
The power consumption of the clock tree dominates over 40% of the total power in high performance VLSI designs. Hence, low power clocking schemes are promising approaches for low power design. We propose energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. These flip-flops operate with a single-phase sinusoidal clock whi...
متن کاملPower reduction on clock-tree using Energy recovery and clock gating technique
Power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. Hence, low power clocking schemes are promising approaches for low-power design. We propose four novel energy recovery clocked flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. Th...
متن کاملLow-swing LC Resonant Clock Distribution Networks Using Conditional Capturing Flip-Flop
The clock distribution network in digital integrated circuits distributes the clock signal which acts as a timing reference controlling data flow within the system. Since the clock signal has highest capacitance and operates at high frequencies, the clock distribution network consumes a large amount of total power in synchronous system. So, a new flip-flop is proposed in a low-swing resonant cl...
متن کامل